Analog Integrated Circuits and Signal Processing
1 MHz–3.5 GHz, wide range input duty 50% output duty cycle corrector
2.5-Gb/s low-jitter low-power monolithically integrated optical receiver
70-MHz IF 10-MHz bandwidth bandpass $$\Upsigma\Updelta$$ modulator for WCDMA applications
A 1 mW power-efficient high frequency CML 2:1 divider
A 1.2 V 10-bit 60-MS/s 23 mW CMOS pipeline ADC with 0.67 pJ/conversion-step and on-chip reference voltages generator
A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC
A 16-channel capacitance-to-period converter for capacitive sensor applications
A 250 MHz low voltage low-pass Gm-C filter
A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme
A four-quadrant analog multiplier under a single power supply voltage
A low power tunable Gm–C filter based on double CMOS inverters in 0.35 µm
A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters
A semi-synchronous SAR ADC
A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters
Analogue CMOS prototype vision chip with prewitt edge processing
Circuit implementation of a fully programmable and continuously slope tunable triangular/trapezoidal membership function generator
Design and implementation of PFM mode high efficiency boost regulator
Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 µm CMOS technology
Design of sub-1-V CMOS bandgap reference circuit using only one BJT
Polyphase analysis filter bank down-converts unequal channel bandwidths with arbitrary center frequencies
Realization of wavelet transform using switched-current filters
Sampled-data IIR filtering via time-mode signal processing
Time-interleaved CMOS chip design of Manchester and Miller encoder for RFID application
Versatile analog squarer and multiplier free from body effect